NXP Semiconductors /LPC43xx /UART1 /RS485CTRL

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Interpret as RS485CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)NMMEN 0 (ENABLED)RXDIS 0 (DISABLED)AADEN 0 (RTS)SEL 0 (DISABLED)DCTRL 0 (LOW)OINV 0RESERVED

DCTRL=DISABLED, SEL=RTS, AADEN=DISABLED, OINV=LOW, RXDIS=ENABLED, NMMEN=DISABLED

Description

RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.

Fields

NMMEN

Multidrop mode select.

0 (DISABLED): Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.

1 (ENABLED): Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt.

RXDIS

Receive enable.

0 (ENABLED): Enabled. The receiver is enabled.

1 (DISABLED): Disabled.The receiver is disabled.

AADEN

Auto Address Detect enable.

0 (DISABLED): Disabled. Auto Address Detect (AAD) is disabled.

1 (ENABLED): Enabled. Auto Address Detect (AAD) is enabled.

SEL

Direction control.

0 (RTS): RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.

1 (DTR): DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.

DCTRL

Direction control enable.

0 (DISABLED): Disabled. Disable Auto Direction Control.

1 (ENABLED): Enabled. Enable Auto Direction Control.

OINV

Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.

0 (LOW): Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.

1 (HIGH): High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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